AnadigmApex RMS to DC Converter

App Note 317 - AnadigmApex RMS to DC Converter

1. Purpose

This application note describes how to use the Delta Sigma Modulator CAM (xDeltaSigmaMod v0.0.9) as part of an RMS-to-DC converter. The original note presents this approach as a way to achieve higher performance than systems using the Multiplier and Divider CAMs that employ the 8-bit SAR.

The reader is introduced to the concepts of the Delta Sigma Modulator CAM, how it works as an ADC solution, how to use it as a multiplier, how to use it as a divider, and finally how to use it to make an RMS to DC converter.

2. Creating the RMS-to-DC Circuit

2.1 Introduction

The DeltaSigmaMod CAM is a second order switched capacitor Delta Sigma modulator. The CAM is composed of two integrators and a comparator as described in the AnadigmDesigner (AD2) CAM help file.

The CAM converts an analog input waveform to a pulse density modulated (PDM) single bit stream, where the density of ones in the serial digital output is proportional to the input signal value. The bit stream can then be low pass filtered to convert to an analog signal (or the pulses can be counted and processed in a microcontroller or DSP).

2.2 Delta Sigma Waveforms

Figure 1 shows the CAM with a simulator signal generator connected to the input and simulator probes connected to the input, output, and clock output.

AD2 Delta Sigma modulator circuit with analog input, digital output, simulator probes, and clock output. — **Figure 1: Delta Sigma ADC CAM**

Figure 2 shows a typical CAM output waveform. The digital signals use 5 V/div, the analog signal uses 1 V/div, and the clock trace is shifted down for clarity. The input is a 1 kHz sine wave with a 3 V amplitude. The Delta Sigma clock has been slowed to 100 kHz to make the waveform easier to see; the PDM output would normally contain much higher digital frequencies.

Simulator traces showing sine-wave input, pulse-density-modulated output, and clock at 100 kHz. — **Figure 2: PDM output for a 1 kHz sine wave with a 100 kHz clock**

Figure 3 shows the output of the same circuit using a 4 MHz clock.

Simulator traces showing the denser PDM output when the modulator clock is increased to 4 MHz. — **Figure 3: PDM output for a 1 kHz sine wave with a 4 MHz clock**

2.3 Delta Sigma Multiplier

The Delta Sigma CAM outputs a single-bit stream that can be used to chop, or multiply, another waveform. Subsequent low-pass filtering yields the analog result. The original note identifies the CAMs required to implement this circuit.

Waveform A drives the Delta Sigma CAM; its output controls a GainSwitch that chops waveform B, followed by a low-pass filter. — **Figure 4: Multiplier circuit**

Waveform A is converted to a Delta Sigma bit stream, which then chops waveform B using a GainSwitch CAM with gains set to +1 and −1. The resulting waveform C is a pulse-density-modulated version of the multiplication A × B. A low-pass filter CAM reveals the analog result at waveform D.

2.4 Delta Sigma Divider

A dividing ADC can be created by adjusting the Delta Sigma reference voltage. The original note uses xDeltaSigmaMod v0.0.9 from the AD2 customer library, which provides access to its reference from within AD2.

Signal A is divided by signal B, which drives the Delta Sigma reference input; GainSwitch and FilterBilinear recover the analog output. — **Figure 5: Divider circuit**

Figure 5 shows signal A being divided by signal B by using B as the Delta Sigma reference voltage. Node 1 (n1) is a PDM version of the division and must be converted back to an analog waveform with a low-pass filter. Because this signal is digital, a GainSwitch CAM first converts it to ±3 V for subsequent processing by the FilterBilinear CAM. Signal D is the analog result of A/B.

2.5 RMS-to-DC Converter

A true RMS converter can be created using both the Delta Sigma multiplier and divider. The original note cites the Linear Technology LTC1966 (March 2002) as a device based on this approach and a paper by Wey and Huang in IEEE Journal of Solid-State Circuits, Volume 35, Number 2, February 2000, for the theory.

Applying the same signal to both inputs of the Delta Sigma multiplier creates the square of the input signal. The remaining circuit creates the mean of the squared voltage. Feeding Vout back to the Delta Sigma reference input divides this mean by Vout, giving the relationship below.

Vout equals the mean of Vin squared divided by Vout; hence Vout equals the square root of the mean of Vin squared, or RMS of Vin. — **RMS conversion relationship**

V_out = mean(V_in²) / V_out
Therefore, V_out = √[mean(V_in²)] = RMS(V_in).

Figure 6 shows the circuit implementing this function.

Complete AD2 RMS-to-DC circuit combining Delta Sigma multiplication and division with zero-crossing detection, window integration, filtering, and feedback. — **Figure 6: RMS-to-DC converter**

The circuit that follows the square function consists of a Zero Crossing detector CAM, an Integrator Hold CAM or window integrator (sometimes referred to as a boxcar integrator), a Sum Filter CAM and a normal integrator CAM. This entire circuit is designed to average the output of the square function.

Finding the average could be achieved by strong low-pass filtering. This circuit instead uses cycle-based integration and feedback. It works by subtracting a voltage V from the squared signal and hunting (using the integrator) for the value of V that gives a zero integration of a complete cycle of the offset signal.

The Integrator Hold (window integrator) is triggered by the zero crossing detector and performs the single cycle integration of the offset (by V) version of the squared signal. The single cycle integration is fed into a (slow) integrator, the output of which is subtracted from the squared signal.

The integrator output will settle at a value for which its input is 0V. Its output will then be the offset voltage that achieves zero integration over a cycle i.e. the average of the original square signal.

Finally the average signal is fed back to the reference input of the Delta Sigma CAM which effectively divides it into the input signal.

3. Testing the RMS-to-DC Circuit

The original application tested a version of the circuit in Figure 6 configured to measure the RMS value of a 60 Hz signal. The CAM settings and parameter values were as follows.

CAM settings for the original 60 Hz test circuit
CAM	Clock	Options	Parameters
xDeltaSigmaMod	4 MHz	Non-inverting; Phase 1; External Reference On	Reference Divisor Factor = 2.0
GainSwitch	4 MHz	Signal Ground; Control High; Phase 1; Half Cycle	Gain1 = +1.0; Gain2 = −1.0
FilterBilinear	4 MHz	Low Pass; Phase 1; Non-inverting; Low Corner Frequency	Corner Frequency = 2.0 kHz; Gain = 2.0
ZeroCross	3.90625 kHz (4 MHz / 256)	Signal Ground; Phase 1; Non-inverted	Threshold = 0 mV
SumFilter	4 MHz	Phase 2; Non-inverting; Non-inverting; Off	Corner Frequency = 4.4 kHz; Gain1 = 1.0; Gain2 = 1.0
IntegratorHold	7.8125 kHz (4 MHz / 128)	Non-inverting; Phase 1; Signal Ground; Control Low	Integration constant = 2.04 × 10⁻⁵ µs⁻¹
Integrator	7.8125 kHz (4 MHz / 128)	Non-inverting; Phase 1; No Reset	Integration constant = 7.81 × 10⁻⁵ µs⁻¹

The circuit was tested using square, sine, and triangle waves over an input amplitude range of 0.1 V to 2 V. Figure 7 compares the measured results with theoretical values calculated using the following formulas:

Triangle wave: V_RMS = V_peak / √3
Sine wave: V_RMS = V_peak / √2
Square wave: V_RMS = V_peak

Measured and theoretical RMS output for triangle, sine, and square waves over input peak amplitudes from 0.1 V to 2 V. — **Figure 7: RMS output versus input amplitude, measured and theoretical**

The original results show good correlation between measured and theoretical values for the different waveforms. The note reports a slight deviation for sine waves above Vpeak = 1.8 V and a larger deviation for square waves above Vpeak = 1.5 V. It attributes this deviation to the output of the square function reaching the internal high rail and clipping.

4. Summary

This application note describes the principles of the Delta Sigma CAM, its use for multiplication and division, and its application in a true RMS-to-DC conversion circuit.

Supporting design files: The original note references accompanying .ad2 circuits under AN231017-U317A. These files are not embedded in the supplied document. Obtain the design files and confirm the availability of xDeltaSigmaMod v0.0.9 before reproducing the application. For assistance, contact Okika Devices Support.