Insights from Dr. Jennifer Hasler at the Energy Consequences of Information Conference
Modern AI systems are running into a hard limit that has nothing to do with algorithms. It is power consumption.
As edge devices, robotics platforms, and embedded ML systems scale in capability, energy efficiency has become the primary constraint in hardware design. Performance gains are increasingly limited not by transistor count, but by how much power a system can afford to consume.
At the Energy Consequences of Information Conference in Santa Fe, researchers and industry leaders gathered to address this challenge directly. A central theme emerged from the discussions. If we want meaningful improvements in energy efficiency, we may need to rethink how computation itself is performed.
Neuromorphic systems, inspired by biological neural architectures, offer one possible path forward.
In her presentation, “Advancing Neuromorphic Hardware Using Recent Advancements in Analog Computing and Tools,” Jennifer Hasler, Professor of Electrical Engineering and pioneer in programmable analog systems, explored how modern analog CMOS infrastructure including Field Programmable Analog Arrays is enabling scalable and energy efficient neuromorphic engineering.
Okika Devices was proud to support this work as a co-sponsor.
The Analog Computing Inflection Point
Digital IC design transformed computing by building abstraction layers, architecture theory, and synthesis tools on top of decades of CMOS scaling. That infrastructure made complex digital systems accessible to a wide engineering base.
Analog computing is now approaching a similar inflection point.
Recent advancements include:
- Large-scale Field Programmable Analog Arrays
- System-level analog and mixed-signal synthesis tools
- Floating-gate programmability in standard CMOS
- Compute-in-Memory architectures
-
Vector-Matrix Multiplication achieving up to 1000× energy efficiency improvements
These developments are moving analog hardware from research prototypes into deployable platforms.
Early commercial FPAA systems, including modern platforms from Okika Devices, demonstrate that programmable analog computing is no longer experimental. Engineers can now prototype reconfigurable analog and mixed signal systems without committing to full custom silicon.
The long term vision mirrors the trajectory of digital design. Provide engineers with practical toolchains, reusable abstraction layers, and scalable hardware infrastructure for complex analog and neuromorphic systems.
When Is Analog Truly Neuromorphic?
Neuromorphic systems often use analog substrates, but not all analog systems are neuromorphic.
True neuromorphic computing:
- Uses event-driven spike-based processing
- Implements neurobiological physical algorithms
- Achieves efficiency or performance beyond traditional analog computation
Spikes alone are not enough. The underlying algorithm must leverage biological computation principles to exceed conventional approaches.
The roadmap extends programmable analog CMOS infrastructure with:
- Silicon-based synapses and dendritic models
- Asynchronous digital support libraries
- Reconfigurable interconnect networks
-
Higher-level abstraction layers for neuromorphic synthesis
This convergence is accelerating the path toward scalable neuromorphic engineering.
Two Engineering Applications Demonstrated
1. Optimal Path Planning via Spike Wave Propagation
Wave propagation of neuron spikes can solve optimal path planning problems using a simple principle.
The first spike to reach the target represents the optimal path.
This approach:
- Solves path planning using polynomial resources
- Operates near NP-boundary optimization problems
- Has implications for robotics and real-time control
- Performs optimization through physical spike dynamics rather than iterative digital computation
Instead of symbolically calculating the solution, the hardware’s physical behavior produces it.
For robotics and autonomous systems operating under strict power constraints, this shift is significant.
2. Energy-Efficient Word Spotting via Dendritic Computation
A second example focused on dendritic coincidence detection and spike timing for signal processing tasks such as word spotting.
This event-driven model enables:
- Precise spike-coded computation
- Sparse and energy-efficient signal processing
-
Computation only when meaningful events occur
By avoiding continuous clocked processing, neuromorphic systems reduce unnecessary switching activity and dramatically lower power consumption.
Why This Matters for Hardware Engineers
For engineers designing embedded and edge systems, this is not theoretical.
Energy consumption now limits:
- Edge AI deployment
- Battery-powered robotics
- Always-on sensing systems
- Compute-in-memory acceleration
- Real-time signal processing in constrained environments
In digital systems, energy cost is dominated by data movement and clocked switching. Scaling frequency or adding cores increases power consumption quickly.
Neuromorphic systems built on programmable analog CMOS offer a different model:
- Physical algorithm execution instead of sequential instruction processing
- Event-driven architectures instead of clocked pipelines
- Reduced data movement through local computation
-
Orders-of-magnitude lower power consumption in specific workloads
This is not about replacing digital systems. It is about identifying classes of problems where physical computation provides measurable energy advantages.
Engineers now have the infrastructure to explore that design space.
The Role of FPAA Platforms
Field Programmable Analog Arrays serve as an accessible entry point into this emerging architecture.
Modern FPAA platforms from Okika Devices provide:
- Large-scale programmable analog fabric
- Floating-gate configurable elements
- Mixed-signal integration capability
- Support for compute-in-memory experimentation
- A practical development environment for neuromorphic prototyping
Instead of committing to custom ASIC fabrication, engineers can prototype neuromorphic architectures directly on reconfigurable analog hardware. This accelerates research, de-risks development, and shortens time to validation.
For R&D teams exploring energy-efficient ML acceleration or biologically inspired hardware, this flexibility is critical.
Rethinking the Energy Limits of Machine Learning
Modern machine learning workloads scale computational demand aggressively, particularly in training and inference at the edge.
Traditional digital approaches respond by increasing parallelism and memory bandwidth, which increases power.
Neuromorphic systems ask a different question: Can we compute differently?
By embedding physical dynamics into hardware and executing algorithms through device-level behavior, programmable analog CMOS opens a path beyond traditional performance and energy tradeoffs.
In certain workloads, neural-inspired hardware can operate thousands of times lower power than comparable digital implementations.
The key is having scalable infrastructure to explore and deploy these architectures.
The Road Ahead
The necessary building blocks are emerging:
- Mature analog synthesis tools
- Programmable analog standard cell libraries
- Neuromorphic abstraction layers
- Design Space Exploration grounded in engineering metrics
The central challenge is translating computational neuroscience into scalable engineering systems suitable for commercial and government applications.
With advancing FPAA technology and programmable analog CMOS infrastructure, practical energy-efficient neuromorphic hardware is moving from research concept to engineering reality.
📩 A copy of Dr. Hasler’s presentation is available upon request.
