Most edge AI systems digitize the entire analog waveform produced by a sensor before determining which parts of the signal contain useful information.
This architecture simplifies software pipelines but introduces a fundamental inefficiency: large volumes of irrelevant data are sampled, converted, processed, and discarded.
The result is unnecessary ADC activity, increased digital workload, and higher energy consumption per inference. In many edge deployments where power, thermal budgets, and battery capacity are constrained, this inefficiency becomes a primary design limitation.
Improving edge AI efficiency is therefore not only a matter of optimizing machine learning models. It also requires reconsidering where feature extraction occurs within the signal chain.
Understanding Inefficiency in Current Edge AI Systems
Most edge AI pipelines follow a similar processing sequence:
Sensor → ADC → Digital Processing → Feature Extraction → Machine Learning → Transmit
Sensors produce continuous analog signals. Analog-to-digital converters (ADCs) sample these signals and convert them into digital form. Digital processors then perform filtering and feature extraction before passing the resulting data to a machine learning model for inference.
In many sensing applications, only a small subset of the captured signal contributes to the final inference decision. Relevant information often appears as spectral features, envelope characteristics, threshold crossings, or transient events embedded within a much larger waveform.
Because the entire signal is digitized first, the system performs significant digital computation on data that is ultimately discarded during feature extraction. This increases processing overhead and raises overall system power consumption.
System-Level Implications of Over-Digitization
Digitizing unnecessary data introduces several system-level trade-offs.
Higher sampling rates increase ADC power consumption. Larger volumes of digital data require additional processor cycles for filtering and preprocessing. Systems must also provision more memory bandwidth and buffering capacity to handle the data flow.
These architectural choices influence hardware selection and system design. Higher digital workloads may require more capable processors, larger batteries, or additional thermal management. In battery-powered or distributed sensing environments, these constraints directly affect deployment scale and operational lifetime.
Addressing this inefficiency requires reconsidering the signal processing architecture itself rather than relying solely on improvements in digital compute performance.
Feature-Level Digitization with FPAA
A more efficient architecture extracts meaningful information from sensor signals before full digitization occurs.
Instead of digitizing the entire waveform, analog signal processing can isolate relevant features at the sensor boundary. Only these features or events are then passed to the digital domain.
This changes the signal chain architecture from:
Sensor → ADC → Digital Processing → ML Inference
to:
Sensor → Programmable Analog Feature Extraction → Digital Processing → ML Inference
Field Programmable Analog Arrays (FPAAs) enable this type of programmable analog preprocessing.
An FPAA is a reconfigurable analog computing device composed of configurable analog cores connected through a programmable routing fabric. Similar to how an FPGA configures digital logic elements, an FPAA configures analog circuit components such as filters, amplifiers, integrators, comparators, and envelope detectors.
Because these functions operate directly in the analog domain, signals can be conditioned and analyzed before digitization occurs.
Typical preprocessing operations implemented in FPAAs include:
- spectral filtering or band isolation
- envelope detection
- threshold and event detection
- analog feature extraction
- adaptive signal conditioning
By extracting features prior to digitization, the system reduces the volume of data entering the digital processing pipeline. Machine learning models receive structured feature inputs rather than raw waveforms.
This architectural shift reduces digital workload while preserving relevant information for inference.
Brute-Force Digital Processing vs Structured Signal Chains
In fully digital architectures, machine learning pipelines must perform several tasks simultaneously:
- noise suppression
- feature extraction
- classification or regression
This often requires larger models and higher computational load.
When feature extraction occurs earlier in the signal chain, the digital system operates on structured inputs that already represent relevant signal characteristics.
Smaller models can perform inference effectively because preprocessing has already isolated meaningful features. The result is lower compute requirements and reduced energy consumption per inference.
Measured and Projected Efficiency Gains with FPAA Architectures
Moving signal processing closer to the sensor boundary can reduce both digital workload and system energy consumption. Several system configurations have been evaluated in published research.
These include:
Baseline Digital Systems
Traditional architectures where sensors feed high-rate ADCs and all preprocessing occurs digitally.
Digital Edge SoCs
Edge-optimized processors designed for embedded machine learning but without analog preprocessing stages.
OKIKA SoC + FPAA Demonstration Systems
Prototype systems combining programmable analog preprocessing with edge SoCs to evaluate hybrid architectures.
Projected Optimized FPAA Architectures
Future integrated designs where analog feature extraction and digital inference are co-optimized within the system architecture.
Experimental demonstrations have shown meaningful reductions in digital workload and inference energy compared with fully digital pipelines. Projected architectures indicate further gains as FPAA integration and toolchains mature.
Energy per Inference
Published prototype systems demonstrate significantly lower energy per inference when analog preprocessing reduces the amount of data entering the digital pipeline.
Early demonstration systems combining FPAA preprocessing with edge processors achieved substantial reductions in energy consumption relative to digital edge SoC implementations. Projected architectures suggest additional improvements as analog preprocessing and ML pipelines are co-designed.
Digital Workload Reduction
Analog feature extraction reduces the number of operations required in downstream digital processing.
Experimental FPAA-based systems have demonstrated large reductions in digital workload by performing filtering and event detection in analog hardware. This allows ML models to operate on a smaller and more structured feature set.
Latency Improvements
Analog preprocessing can also reduce inference latency.
In traditional digital pipelines, buffering and high-rate sampling introduce delays before the signal reaches the machine learning model. Feature extraction in the analog domain allows events to be detected and forwarded to the digital system immediately.
Prototype FPAA front-ends have demonstrated near real-time responses, while projected architectures indicate sub-millisecond latency in certain sensing applications.
Applications That Benefit from Analog Feature Extraction
Analog preprocessing is particularly useful in sensing applications where meaningful information appears as structured features or sparse events within a larger analog signal.
Examples include:
- acoustic anomaly detection
- vibration-based predictive maintenance
- biosignal monitoring such as ECG or EMG
- RF and radar sensing
- always-on sensor monitoring systems
These domains often require continuous sensing but only sporadic inference events. Feature-level digitization allows systems to monitor signals efficiently without continuously processing large digital data streams.
Compute Moving Toward the Sensor
Edge computing has progressively moved computation closer to the data source. Historically, most processing occurred in centralized cloud infrastructure.
Edge processors now perform inference locally, reducing latency and network dependence. The next architectural step is to move certain signal processing functions even closer to the sensor.
Programmable analog preprocessing allows sensing systems to operate efficiently with reduced data movement, lower digital workload, and minimal transmission requirements. In distributed sensing environments, these properties enable longer device lifetimes and greater deployment scalability.
The Future of Efficient Edge AI
In architectures that incorporate programmable analog preprocessing, the signal chain becomes:
Physical World → Sensors → FPAA → Digital Processor → ML Inference → Applications
The FPAA performs feature extraction directly on analog signals, reducing the volume of data entering the digital domain. Digital processors can therefore focus primarily on inference rather than preprocessing.
As sensing systems continue to expand across industrial, medical, and environmental monitoring applications, energy efficiency and system-level architecture will play an increasingly important role.
Systems that digitize entire waveforms push significant computational load into digital processors. Architectures that extract features before digitization reduce ADC activity, digital workload, and inference energy simultaneously.
For many sensing applications, the most important architectural decision is not the machine learning model itself but where feature extraction occurs in the signal chain.
Sources
Hasler, J., “The Potential of SoC FPAAs for Emerging Ultra-Low-Power Machine Learning,” J. Low Power Electron. Appl., vol. 12, no. 2, 2022.
Ige, A., Yang, L., Yang, H., Hasler, J., & Hao, C., “Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing,” J. Low Power Electron. Appl., vol. 13, no. 4, 2023.
Belostotski, L., “A Survey of Analog Computing for Domain-Specific Applications,” Electronics, vol. 14, no. 16, 2025.
Hasler, J. & Ayyappan, P.R., “An Analog Architecture and Algorithm for Efficient Convolutional Neural Network Image Computation,” J. Low Power Electron. Appl., vol. 15, no. 3, 2025.
